Low-power Design of Adiabatic Dynamic CMOS Logic using Parasitic Capacitance of 0.18μm Standard CMOS Model
نویسندگان
چکیده
In this paper, the influence on the load capacitance value of the adiabatic dynamic CMOS logic (ADCL) is examined. The adiabatic operation and reduction effect of power consumption are confirmed using LTspice with 0.18μm standard MOS model. Furthermore, the 3-bit digital PWM using ADCL without voltage holding capacitance (CS) was simulated for the organic light emitting diodes (OLEDs) dimming systems. The power consumption of the ADCL digital PWM without Cs for all bit patterns decreased by 52.3 % compared to that of the ADCL PWM with CS.
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